LTC4252A-1IMS#TRPBF【PDF 24/36 页】IC CNTRLR HOTSWAP NEGVOLT 10MSOP

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LTC4252-1/LTC4252-2

LTC4252A-1/LTC4252A-2

425212fe

For more information www.linear.com/LTC4252-1

applicaTions inForMaTion

Undervoltage Timing

In Figure 11 when UV pin drops below V

UVLO

(time point?),

the LTC4252 shuts down with TIMER, SS and GATE all

pulling low. If current has been flowing, the SENSE pin

voltage decreases to zero as GATE collapses. When UV

recovers and clears V

UVHI

(time point 2), an initial timer

cycle begins followed by a GATE start-up cycle.

Undervoltage Lockout Timing

The V

undervoltage lockout comparator, UVLO, has a

similar timing behavior as the UV pin timing except it looks

for V

< (V

LKO

LKH

) to shut down and V

> V

LKO

start. In an undervoltage lockout condition, both UV and

OV comparators are held off. When V

exits undervoltage

lockout, the UV and OV comparators are enabled.

Undervoltage Timing with Overvoltage Glitch

In Figure 12, both UV and OV pins are connected together.

When UV clears V

UVHI

(time point 1), an initial timing

cycle starts. If the system bus voltage overshoots V

OVHI

as shown at time point 2, TIMER discharges. At time point

3, the supply voltage recovers and drops below the V

OVLO

threshold. The initial timing cycle restarts, followed by a

GATE start-up cycle.

Overvoltage Timing

During normal operation, if the OV pin exceeds V

OVHI

shown at time point 1 of Figure 13, the TIMER and PWRGD

status are unaffected. Nevertheless, SS and GATE pull down

and the load is disconnected. At time point 2, OV recovers

and drops below the V

OVLO

threshold. A GATE start-up

cycle begins. If the overvoltage glitch is long enough to

deplete the load capacitor, a full start-up cycle as shown

between time points 4 through 7 may occur.

Circuit Breaker Timing

In Figure 14a, the TIMER capacitor charges at 230礎 if

the SENSE pin exceeds V

but V

DRN

is less than 5V . If

the SENSE pin drops below V

before TIMER reaches

TIMER

GATE

SENSE

DRAIN

PWRGD

5.8礎

58礎

5.8礎

58礎

UV DROPS BELOW V

UVLO

. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES

3 4 56 7 89

TIMER CLEARS V

TMRL

, CHECK GATE < V

GATEL

, SENSE < V

AND SS < 20 " V

1011

425212 F11

UV CLEARS V

UVHI

, CHECK OV CONDITION, GATE < V

GATEL

, SENSE < V

, SS < 20 " V

AND TIMER < V

TMRL

ACL

230礎 + 8 " I

DRN

20 " V

GATEH

DRNL

DRNCL

20 " (V

+ V

)

20 " (V

ACL

+ V

)

GATEL

TMRL

TMRH

UVHI

UVLO

GATE

START-UP

INITIAL TIMING

Figure 11. Undervoltage Timing (All Waveforms Are Referenced to V

)

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